Field
Implementations described herein generally relate to semiconductor manufacturing and more particularly to methods for etching a low-k dielectric barrier layer disposed on a substrate using a non-carbon based approach.
Description of the Related Art
As the feature size of the device patterns get smaller, the critical dimension (CD) requirement of features becomes a more important criterion for stable and repeatable device performance. Allowable CD variation across a substrate has also scaled with the scaling of feature CD. With lateral dimensions scaling faster than vertical dimensions, because of issues such as device capacitance, high aspect ratios (HAR) are now prevalent in the industry. When such demanding aspect ratios and CD control are compounded with requirements of high etch selectivity, sidewall smoothness and high tool throughput, the process window for any hardware configuration can become very small. In many situations, a small process window can be found only when a number of process gases are incorporated into a complex etchant gas mixture combined with extreme hardware settings, such as very high RF bias powers, to achieve a fragile balance between sidewall passivation, etch rate and mask selectivity. However, such small process windows typically suffer from performance limitations which cannot be tuned out of the etch process with known means.
Fabrication techniques often now employ a mask stack that includes non-photo definable material layers disposed below a photo definable layer (i.e., a photoresist). The non-photo definable material layers may include a low-k dielectric material such as a silicon carbide based material. One example of such a silicon carbide based material is BLOk™ (barrier low-k) film, which is available from Applied Materials, Inc. of Santa Clara, Calif.
Currently, low-k barrier layers are typically etched using carbon fluoride process gases; however, these carbon fluoride-containing chemistries often form etching defects that degrade the structure. These etch-related defects commonly include faceting, micro-trenching, critical dimensions (CD) bias, micro-loading, striations, and sloped sidewalls. The terms “faceting” and “micro-trenching” are used herein to refer to the undesirable overetching of an edge of the via hole and a corner region of the trench, and the terms “critical dimensions (CD) bias” relates to a difference between critical dimensions of the opening or trench and their respective elements of the etch mask. Correspondingly, the term “micro-loading” refers to a difference in etch rates in the areas having different device density, while the terms “striations” and “sidewall slope” describe, respectively, surface roughness and vertical profiles of the opening or trench. These etch-related defects may affect performance and increase costs of devices that include such structures.
Therefore, there is a need for improved processes for etching low-k barrier layers.